1. Field
Example embodiments relate to a nonvolatile memory device and a method of fabricating the same. Other example embodiments relate to a nonvolatile memory device including an oxide layer having a resistance gradient, which unifies current paths in the oxide layer by forming a nano dot in the oxide layer, and a method of fabricating the same.
2. Description of the Related Art
Research has been conducted to enhance the integration density of semiconductor devices, for example, semiconductor memory devices. As the integration density is enhanced, the memory capacity per unit area of the memory devices may be improved. Research has also been conducted on driving the device at relatively low power and improving the operation speed thereof. A general semiconductor memory apparatus may include many unit memory cells connected by circuits. Semiconductor memory devices may be classified as volatile memory devices and nonvolatile memory devices.
A dynamic random access memory (DRAM) may be a typical volatile semiconductor memory device. In DRAMs, the unit memory cells may include one switch and one capacitor and DRAMs may have relatively high integration density and relatively fast operating speeds. Because DRAM is a volatile memory device, stored data may be lost when the power is turned off.
Flash memory may be an example of a nonvolatile memory device capable of maintaining stored data after the power is turned off. Unlike DRAMs, flash memory may be nonvolatile, but it may have relatively low integration density and relatively slow operating speed, compared to DRAMs. Research is being done with respect to nonvolatile memory devices (e.g., a magnetic random access memory (MRAM), ferro-electric random access memory (FRAM), phase-change random access memory (PRAM) and/or resistive random access memory (RRAM)).
MRAM may store data by a change in magnetization direction in a magnetic tunnel junction, and FRAM may store data by using the polarization characteristic of ferroelectrics. Each may have merits and demerits, but both have been developed for relatively high integration density, relatively high-speed operation, relatively low-power driving and improved data retention.
PRAM may store data by a change in resistance value according to a phase change and may use a chalcogenide resistor. The memory device may be formed by utilizing the higher resistance of an amorphous state compared to a crystalline state. When PRAM is fabricated by using a conventional semiconductor device fabrication process, etching may be difficult and a relatively long fabrication time may be required. The unit cost of a product may increase due to relatively low productivity, thereby decreasing price competitiveness.
RRAM may use a transition metal oxide as a data-storing layer. RRAM may utilize the resistance-changing characteristic of RRAM in that a resistance value may vary according to an applied voltage. FIGS. 1A and 1B illustrate a conventional structure of a RRAM and current paths formed in an oxide layer by the applied voltage.
In FIGS. 1A and 1B, the RRAM may include an oxide layer 12 and an upper electrode 13 sequentially formed on a lower electrode 11. The lower electrode 11 and the upper electrode 13 may include a metal (e.g., iridium (Ir), ruthenium (Ru), gold (Au), platinum (Pt) and/or an oxide thereof), which is generally used as an electrode of a memory device. The oxide layer 12 may include a transition metal oxide having the resistance-changing (variable resistance) characteristic. The oxide layer 12, as a data-storing layer, may record or reproduce data when the voltage is applied to the oxide layer 12 through the lower and upper electrodes 11 and 13.
When the voltage is applied to the oxide layer 12 through the lower and upper electrodes 11 and 13, a current may flow through the oxide layer 12 due to an electrical potential difference. The current may not flow uniformly in all regions of the oxide layer 12. The flowing current may form momentary current paths 10 in the oxide layer 12 through grain boundaries. As the current paths 10a and 10b formed in the oxide layer 12 are randomly formed, the formation position and number of current paths 10a and 10b may change even if the same voltage is applied to the oxide layer 12 through the lower and upper electrodes 11 and 13. It may be known that the current paths 10a in FIG. 1A and the current paths 10b in FIG. 1B are different from each with respect to their formation position and number.
FIG. 2 is a graph comparing the current value in an applied voltage value when the voltage is applied to a lower electrode and an upper electrode in a memory device, including an oxide layer, formed of a general resistance-changing material. FIG. 2 illustrates the value of current flowing in the oxide layer 12 when a desired voltage is applied to the lower and upper electrodes 11 and 13 of the RRAM of FIGS. 1A and 1B. For example, the oxide layer 12 may include a nickel oxide NiO, and the lower and upper electrodes 11 and 13 may include Pt.
In FIG. 2, the value of current flowing in the oxide layer 12 may be measured while the voltage applied to the lower and upper electrode 11 and 13 gradually increases from about 0V. From the measurement results, it may be noted that the current value to the applied voltage may not be regular and may be different according to the time of measurement. The change in a reset current (RC) may be ten times that of the reset current before the same voltage is applied. The value of a set voltage (SV) may not be maintained. Such unstable results may be the result of the irregular current path distribution in the oxide layer 12. When the RC value is unstable and relatively high, the reliability of the semiconductor memory device may be relatively low and power consumption may increase.
In the conventional memory device of FIGS. 1A and 1B, because the current paths are different whenever the voltage is applied, the current value in the reset state may be irregular.